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shanghai belling corp., ltd bl24c32/64 1 bl24c32/BL24C64 32k bits (4096 x 8) / 64k bits ( 8192 x 8) t w o-wire serial eeprom features two-wire serial interface v cc = 1.8v to 5.5v bi-directional data transfer protocol internally organized bl24c32, 4096 x 8 (32k bits) BL24C64, 8192 x 8 (64k bits) 400 khz (1.8v, 2.7v,5v) compatibility 32-byte page (32k/64k) write modes partial page writes allowed self-timed write cycle (5 ms max) high-reliability 1 million write cycles guaranteed data retention > 100 years operating temperature: -40 to +85 8-lead pdip, 8-lead sop and 8-lead tssop packages pin configuration description bl24c32/BL24C64 provides 32768/65536 bits of serial electrically erasable an d programma ble read-only me mor y ( eeprom) organized as 4096 words of 8 bits each. the device is op timized for use in many industr ial and commercial app lica t ions where low-power and low-voltage operatio ns are e sse ntial. the bl24c32/BL24C64 is available in spa c e-saving 8-lead pdip, 8-lead sop, and 8-lea d tssop p a ckages a n d is a ccessed via a two-wire serial interface.
shanghai belling corp., ltd bl24c32/64 2 pin descriptions pin number designation type name and functions 1 ? 3 a0 - a2 i address inputs device/page addresses (a2, a1, a0) : the a2, a1 and a0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other 24cxx devices. when the pins are hardwired, as many as eight 32k/64k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). if the pins are left floating, the a2, a1 and a0 pins will be internally pulled down to gnd if the capacitive coupling to the circuit board vcc plane is <3 pf. if coupling is >3 pf, recommends connecting the address pins to gnd. 5 sda i/o & open-dr ain serial data serial data (sda): the sda pin is bi-directional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of other open-drain or open- collector devices. 6 scl i serial clock input serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. 7 wp i write protect write protect (wp): the write protect input, when connected to gnd, allows normal write operations. when wp is connected high to vcc, all writ e operations to the memory are inhibited. if the pin is left floating, the wp pin will be internally pulled down to gnd if the capacitive coupling to the circuit board vcc plane is <3 pf. if coupling is >3 pf, recommends connecting the pin to gnd. switching wp to vcc prior to a write operation creates a software write protect function. the write protection feature is enabled and operates as shown in the following ta b l e 1 . 4 gnd p ground 8 vcc p power supply table 1: write protect part of the array protected wp pin status: 24c32 24c64 at vcc full (32k) array full (64k) array at gnd normal read/write operations
shanghai belling corp., ltd bl24c32/64 3 block diagram functional description 1. memory organization 2 4 c 3 random word addressing requires a 12-bit dat a word address. 2 , 3 2 k s e r i a l eeprom: the 32k is internally organiz ed as 128 p ages of 32 bytes each. 24c64, 64k serial eeprom: the 64k is internally organiz ed as 256 p ages of 32 bytes each. random word addressing requires a 13-bit dat a word address. 2. device operation c l oc k and d a t a transition s : t he sda pi n is n o rmall y pul le d hig h w i th an e x ternal devic e. data o n th e sda pi n ma y c han ge onl y dur ing s c l l o w ti me per iods (s e e f i gur e 1). d a ta chan ges dur ing s c l h i g h p e rio d s w i ll indicate a start or stop condition as defined below .
shanghai belling corp., ltd bl24c32/64 4 star t co n d ition : a high-to-lo w trans iti on of sda w i th scl hi gh is a start conditio n w h ich must pre c ede a n y other command (see f i gure 2 ) . stop co ndition: a lo w - t o -hi gh transitio n of sda w i th scl hig h is a stop conditi on. after a read seque nce, the stop command w ill place the eeprom in a standby pow er mode (see figure 2) a ckn ow led g e: all addr esses a nd data w o rds are ser i all y tra n smitted to and from th e eeprom in 8-bit w o rds. t he eeprom sends a ?0? to ackno w l e dg e that it has rece i v ed eac h w o rd. t h is happe ns duri ng the ni nth clock c y cl e. standby mode: t he 24c32/2 4 c6 4 fea t ures a lo w - po w e r stand b y mode w h ich is e nab led: (a) u p o n po w e r-u p and (b) after the receipt of the st op bit and the completion of any internal operations memory reset: after an interr upti on i n protoc ol, p o w e r loss or s y ste m reset, an y t w o- w i re part c a n be res e t b y follow i ng these steps: 1. clock up to 9 cy cles. 2. look for sda high in each cy cle w h ile scl is high. 3. create a start condition. figure 1 . data validity figure 2. s t art and s t op definition
shanghai belling corp., ltd bl24c32/64 5 figure 3. output acknowledge 3. device addressing the 32k/64k eeprom devic e s all require an 8-bit dev ic e addres s word following a s t art c o ndition to enable the chip for a read or write operation (see figure 4). the devi c e a ddre s s word con s i s ts of a mandato r y ?1 ?, ?0 ? seq uen ce for the first four mo st sig n ificant bits as s hown. this is c o mmon to all the serial eeprom devic es . the 32k/64k uses the three device address bit s a2, a1 , a0 to allow as many as eight devices on the same bus. these bit s must comp are to their co rresponding hardwired input pins. the a2, a1, and a0 pins use an internal propriet a ry circui t that biases them to a logic low condition if the pins are allowed to float. the ei ghth bit of the devi c e add re ss i s th e re ad/write o peratio n sele ct bit. a re ad operation i s i n itiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the dev ice addres s, the eeprom will output a ?0?. if a com p are is not made, the chi p will return to a standby state. noise protection: s pecial internal circuitry placed on t he sda and scl pins prevent small noise spikes from activating the device. da t a security : the 24c32/24c64 has a hardware dat a protecti on scheme that allows the user to write protect the entire memory when the wp pin is at vcc. 4. w r ite operations byte writ e: a write op eration requi res an 8 - bit da ta word a ddress followin g the device ad dre ss word and acknowledgment. upon recei p t of th is address, the eeprom will again respond with a ?0? and then clock i n the first 8-bit data word. followi ng recei p t of the 8-bit data word, the eeprom will output a ?0? and the addressing device, such a s a microcontroll er, must term inate t he write sequ en ce with a sto p con d ition. at this time the e eprom ent e r s a n intern all y timed write cycle, t wr , to the nonvol atile memo ry. all inputs are disabled during thi s wri t e cycle an d the eeprom will not respond until t he write is complete (see figure 5).
shanghai belling corp., ltd bl24c32/64 6 page write: the 32k/64k devices are capable of 32-byte page writes. a page write i s initiated the same as a b y te write, but the microcont rolle r doe s n o t send a stop con d ition after the first data word i s clock ed in. instead, after t he eeprom ackn owledges recei p t of the first data word, the mi crocontroller can transmit up to 31 mo re data words. the eeprom will respond with a ?0? after each da ta word re cei v ed. the microco n trolle r must terminate the page writ e seque nce with a stop condition (see figure 6). the data word address lo wer five (32k/ 64k) bits a r e internally in cremented follo wing the rece ipt of each data wo rd. t he high er d a t a word ad dress bits a r e not increme n t ed, retainin g the memo ry page ro w locatio n . whe n the wo rd a d d re ss, inte rna lly generat ed, rea c he s the page b oun da ry, the followi ng byte is placed at the beginning of the same page. if more than 32 data word s are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. ackno w le dge polli ng: once the internally timed write cy cle has started and the eeprom inputs are di sa bled, ackno w le dg e polling ca n be initiated. th is involve s sen d ing a st art co ndition followe d by the device ad dre s s word. t he read/ write bit is rep r e s e n ta tive of the operation desired. o n ly if the interna l write cy cle h a s complete d will the eeprom respon d with a ?0?, allowin g the read or write seq uen ce to continue. 5. read operations rea d ope rati ons a r e initiat ed the same way as writ e operation s wi th the exc epti on that the read/write sele ct bit in th e device add ress word is set to ?1 ?. there are three re ad operat ion s : curre nt address read, random address read and sequential read. c urrent address re ad: the int e rnal d a ta word ad dre s s cou n ter main tains the last addre s s acce ssed during the last re ad or wr ite op eration, incre m ented by one. this addre ss stay s valid betwee n operation s a s long a s th e chip po we r i s maintaine d . t he ad dre s s ?roll over? du rin g re ad i s fro m the la st byte of the la st memory pa ge to the first byte of t he first page. the address ?roll over? du ring write is from the last byte of the cur- rent page to the first byte of the same page. once the dev ice ad dre s s with the rea d /write sele ct bi t set to ?1? is clo c ked in an d ackno w led ged by the eeprom, the c u rrent address data word is s e rially c l ock ed out. the mic r oc ontroller does not res p ond with an input ?0? but does generate a following stop condition (see figure 7). r and om rea d : a ran d o m re ad req u ire s a ?du m my? byte write se que nce to load i n the data word address. o n ce the d e vice address wo rd and data wo rd add re ss a r e clo c ked i n an d ackn owl edg ed by th e eeprom, the mic r ocontroller mus t gen erate another s t art c o ndition. t he microcontroller now initiates a current address read by sending a dev ice address with t he read/write select bit high. the eeprom ackno w le dge s the device address an d seri ally clo c ks out the dat a wo rd. the microcontroll er doe s no t respond with a ?0? but does generate a following stop condition (see figure 8). sequenti a l rea d : se quential rea d s a r e initiate d by eithe r a cu rre nt add ress read or a ra ndom address rea d . after the micro c o n troll e r receives a da ta word, it respond s with an ackno w led ge. as long as the eeprom receives an acknowl edge, it will c ontinue to i n crement the data word address and seri ally clo c k out sequ enti a l data wo rd s. whe n t he memory ad dress limit is reached, the data wo rd address will ?roll ove r? a nd the seq u ential rea d will contin ue. the sequ ential rea d o peratio n is terminate d when the microco n trolle r d oes not re sp ond with a ?0? but doe s gene rate a followin g stop condition (see figure 9) figure 4. d e v i ce address
shanghai belling corp., ltd bl24c32/64 7 figure 5. by te w r ite figure 6. page w r ite figure 7. current address read figure 8. random read figure 9. sequential read
shanghai belling corp., ltd bl24c32/64 8 electrical characteristics
shanghai belling corp., ltd bl24c32/64 9 ac electrical characteristics applica b le ov er re com m en ded op eratin g range from t a = ?40 c to + 8 5 c , vcc = +1.8v to + 5 .5v , c l `` = 1 ttl gate and 100 pf (unless otherwise noted) 1.8, 2.7, 5.0-volt p a r a m e t e r s y m b o l m i n . t y p . m a x . unit s clock frequency , scl f scl - - 4 0 0 k h z clock pulse wid t h low t low 1.2 - - s clock pulse wid t h high t hi gh 0.6 - - s noise suppression t i me t i - - 5 0 n s clock low to dat a out v a lid t aa 0.1 - 0 . 9 s t i me the bus mu st be fr ee before a n e w transmission can st art t buf 1.2 - - s st a r t h o l d t i m e t hd. st a 0.6 - - s s t art setup t i me t su.st a 0.6 - - s dat a in hold t i me t hd. da t 0 - - s dat a in setup t i me t su.da t 100 - - n s input s rise t i me t r - - 0 . 3 s input s fall t i me t f - - 3 0 0 n s s t op setup t i me t su.st o 0.6 - - s dat a out hold t i me t dh 50 - - n s w r ite cycle t i me t wr - - 5 m s 5.0v , 25 c, byte mode ` enduran ce 1m - - wr i t e cyc l es bus t i ming figure 10. scl: serial cloc k , sda: serial dat a i/o
shanghai belling corp., ltd bl24c32/64 10 w r ite cy cle t i ming figure 11. scl: serial cloc k , sda: serial data i/o note: 1. the write cycle time t wr is the time from a valid stop c ondition of a write se quence to th e end of the internal clear/write cycle.
shanghai belling corp., ltd bl24c32/64 11 package information pdip outline dimensions note: 1. this dra w ing is for general info rmation only; refer to jedec drawing ms-001, v a riation ba for additional information. 2. dimensions a and l are measured with the p a ckage seated in jedec seating plane gauge gs-3. 3. d, d1 an d e1 dimensions do not include mold flash or pr otrusions. mold fla s h or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tip s are preferred to ease insertion. 6. b2 and b3 maxi mum dimensions do not include damba r protrusion s. damba r protrusions shall not exceed 0.010 (0.25 mm).
shanghai belling corp., ltd bl24c32/64 12 jedec soic note: 1. these dr a w ings are for gener a l informatio n only . r e fer to jedec dr a w ing ms-012, v a riation aa for proper dime nsions, toler a nces, datums, etc.
shanghai belling corp., ltd bl24c32/64 13 tssop note: 1. this dr a w ing is for gener a l information only . r e fer to jedec dr a w ing mo-153, v a riation aa, for proper di mensions, toler a nces, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs sha ll not ex ceed 0.15 mm (0.006 in) per side . 3. dimension e1 does not include inter - lead flash or protrusions. inter - lead flash and protrusions shall not ex ceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allow a ble dambar protrusion shall be 0.08 mm total in ex cess of the b dimension at maximum material condition. dambar cannot be located on the lower r a dius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h.

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